TSMC's CoWoS packaging capacity is rumored to reach at least 200,000 wafers per month (wpm) by 2027, up from 130,000 wpm in 2026, as the company accelerates plant construction with 24-hour shifts. NVIDIA reportedly reserves over 50% of current CoWoS capacity and most of TSMC's SoIC packaging capacity, which is ramping to an estimated 50,000 wpm in 2027. AMD has diversified 50% of its orders to OSATs like ASE, SPIL, and Amkor due to insufficient CoWoS access.
Advanced packaging capacity remains a binding constraint for AI chip supply, with TSMC prioritizing NVIDIA and other hyperscalers, forcing competitors to diversify to OSATs.